CS211 Digital Logic (H)

Summer 2021


Dr. James Jianqiao Yu 余剑峤

Course Description

This is a foundational course in digital design that aims to provide an understanding of the fundamental concepts, circuits in digital design, and expose students to the mainstream approaches and technologies used in digital design. Digital logic is the representation of signals and sequences of a digital circuit through numbers. It is the basis for digital computing and provides a fundamental understanding on how circuits and hardware communicate within a computer. Digital logic is typically embedded into most electronic devices, including calculators, computers, and watches. This field is utilized by many careers that work with computers and technology. Although most modern logic design is now achieved with computerized methods, this course covers the essential building blocks upon which modern techniques were developed. This course introduces the core logical operations and demonstrates elementary methods to design logic circuits to achieve a desired function. This course also introduces the fundamentals of combinational and sequential circuits, with their high-level implementations as demonstrations. This course allows students to gain hands-on experience by building computer hardware through the use of algorithms and simple inputs. They learn how simple inputs of ones and zeros can be used to store information on computers, including documents, images, sounds, and videos.Students should be able to demonstrate an in-depth knowledge of the fundamental concepts and issues and the engineering principles involved in digital design and be able to design a series of combinational and sequential circuits. In addition, they should demonstrate through hands-on experimentation knowledge of the digital design process using HDLs.


Course Materials

There is no required text for this course. Lecture notes and lab sheets will be posted periodically on this page. There are three reference textbooks:

  • Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog by M. Morris Mano et al.
  • Digital Principles and Logic Design by A. Saha and N. Manna.
  • Digital Logic Design by B. Holdsworth and C. Woods.


Labs will be organized every week starting from the first one and a few coding questions need to be solved. There will be four written assignments, a mid-term and a final examination. The assignments will focus on digital logic theory. We try very hard to make questions unambiguous, but some ambiguities may remain. Ask if confused or state your assumptions explicitly. Reasonable assumptions will be accepted in case of ambiguous questions.

Grade Breakdown

  • 10% Lecture attendance
    • Lecture attendance will be recorded by ad-hoc quizzes.
  • 20% Lab and project
  • 20% Assignments
    • 5% for each assignment. 50% penalty applies for late submission within 24 hours. No submission is allowed after 24 hours.
  • 15% Mid-term examination
  • 35% Final examination

Schedule and Syllabus

Unless otherwise specified the lectures are 2:00pm to 3:50pm every Monday, Tuesday, and Thursday at Room 406, Bldg. 6, Lychee Hill, SUSTech. The last week will have an additional one on Friday at the same time. The lab sessions are 4:20pm to 6:10pm on the same day.

Event Date Description Materials
Lecture #1 Monday, Jun. 21 [0] Course Introduction
[1] Binary Numbers
[slides] [lab]
Lecture #2 Tuesday, Jun. 22 [2] Boolean Algebra and Logic Gates [slides] [lab]
Lecture #3 Thursday, Jun. 24 [3] Gate‐Level Minimization [slides] [lab]
Lecture #4 Monday, Jun. 28 [4] Two‐Level Implementation [slides] [lab]
Lecture #5 Tuesday, Jun. 29 [5] Combinational Logic [slides] [lab]
Deadline Wednesday, Jun. 30 Assignment #1 Due
Lecture #6 Thursday, Jul. 1 [5] Combinational Logic [lab]
Lecture #7 Monday, Jul. 5 [6] Latches and Flip-flops [slides] [lab]
Lecture #8 Tuesday, Jul. 6 Mid-term Examination [lab]
Deadline Wednesday, Jul. 7 Assignment #2 Due
Lecture #9 Thursday, Jul. 8 [7] Synchronous Sequential Logic [slides] [lab]
Lecture #10 Monday, Jul. 12 [7] Synchronous Sequential Logic [lab]
Lecture #11 Tuesday, Jul. 13 [8] Arithmetic Circuits [slides] [lab]
Deadline Wednesday, Jul. 14 Assignment #3 Due
Lecture #12 Thursday, Jul. 15 [9] Registers [slides] [lab]
Lecture #13 Monday, Jul. 19 [9] Registers [lab]
Lecture #14 Tuesday, Jul. 20 [A] Counters [slides] [lab]
Deadline Wednesday, Jul. 21 Assignment #4 Due
Lecture #15 Thursday, Jul. 22 [B] Programmable Logic Devices [slides]
Lecture #16 Friday, Jul. 23 Revision