CS207 Digital Logic

Spring 2021


Dr. James Jianqiao Yu 余剑峤

Course Description

This is a foundational course in digital design that aims to provide an understanding of the fundamental concepts, circuits in digital design, and expose students to the mainstream approaches and technologies used in digital design. Digital logic is the representation of signals and sequences of a digital circuit through numbers. It is the basis for digital computing and provides a fundamental understanding on how circuits and hardware communicate within a computer. Digital logic is typically embedded into most electronic devices, including calculators, computers, and watches. This field is utilized by many careers that work with computers and technology. Although most modern logic design is now achieved with computerized methods, this course covers the essential building blocks upon which modern techniques were developed. This course introduces the core logical operations and demonstrates elementary methods to design logic circuits to achieve a desired function. This course also introduces the fundamentals of combinational and sequential circuits, with their high-level implementations as demonstrations. This course allows students to gain hands-on experience by building computer hardware through the use of algorithms and simple inputs. They learn how simple inputs of ones and zeros can be used to store information on computers, including documents, images, sounds, and videos.Students should be able to demonstrate an in-depth knowledge of the fundamental concepts and issues and the engineering principles involved in digital design and be able to design a series of combinational and sequential circuits. In addition, they should demonstrate through hands-on experimentation knowledge of the digital design process using HDLs.


Course Materials

There is no required text for this course. Lecture notes and lab sheets will be posted periodically on this page. There are three reference textbooks:

  • Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog by M. Morris Mano et al.
  • Digital Principles and Logic Design by A. Saha and N. Manna.
  • Digital Logic Design by B. Holdsworth and C. Woods.


Labs will be organized every week starting from the first one and a few coding questions need to be solved. There will be five written assignments, a mid-term and a final examination. The assignments will focus on digital logic theory. We try very hard to make questions unambiguous, but some ambiguities may remain. Ask if confused or state your assumptions explicitly. Reasonable assumptions will be accepted in case of ambiguous questions.

Grade Breakdown

  • 10% Lecture attendance
    • At least ten lecture attendance, 1% each, is required including the pre-LNY weeks.
  • 10% Lab attendance
    • There will be ad-hoc attendance records.
  • 20% Assignments
    • 5% for each assignment. 50% penalty applies for late submission within 24 hours.
  • 20% Mid-term examination
  • 40% Final examination

Schedule and Syllabus

Unless otherwise specified the lectures are Friday 2:00pm to 3:50pm at Room 403, Bldg. 6, Lychee Hill, SUSTech. The lab sessions are Friday 4:20pm to 6:10pm at Room 402, Bldg. 6, Lychee Hill, SUSTech.

Event Date Description Materials
Week #1 Friday, Jan. 15 Course Introduction and Binary Numbers [slides] [lab]
Week #2 Friday, Jan. 22 Boolean Algebra and Logic Gates [slides] [lab]
Week #3 Friday, Mar. 5 Gate‐Level Minimization [slides] [lab]
Week #4 Friday, Mar. 12 Two‐Level Implementation [slides] [lab]
Event Sunday, Mar. 14 Assignment 1 Release (Weeks 1 to 4) [problems]
Week #5 Friday, Mar. 19 Combinational Logic I [slides] [lab]
Week #6 Friday, Mar. 26 Combinational Logic II [slides] [lab]
Deadline Friday, Mar. 26 Assignment #1 Due
Event Sunday, Mar. 28 Assignment 2 Release (Weeks 5 and 6) [problems]
Week #7 Friday, Apr. 2 Latches and Flip-flops [slides] [lab]
Week #8 Friday, Apr. 9 Mid-term Examination
Deadline Friday, Apr. 9 Assignment #2 Due
Week #9 Friday, Apr. 16 Synchronous Sequential Logic I [slides] [lab]
Week #10 Friday, Apr. 23 Synchronous Sequential Logic II [slides] [lab]
Event Sunday, Apr. 25 Assignment 3 Release (Weeks 7 to 10) [problems]
Week #11 Friday, Apr. 30 Arithmetic Circuits I [slides] [lab]
Week #12 Friday, May 7 Arithmetic Circuits II [slides] [lab]
Deadline Friday, May 7 Assignment #3 Due
Event Sunday, May 9 Assignment 4 Release (Weeks 11 to 13) [problems]
Week #13 Friday, May 14 Registers and Counters [slides] [lab]
Week #14 Friday, May 21 Programmable Logic Devices [slides] [lab]
Deadline Friday, May 21 Assignment #4 Due
Week #15 Friday, May 28 Revision [slides] [lab]